A Two-Level Power-Grid Model for Transient Current Testing Evaluation

Abstract

We evaluate the possibilities of transient current testing practical implementation by comparing the transient supply current signature at the IC supply pins to its internal behavior. This analysis is key to correlate the internal circuit block transient current shape to the waveform measured outside the IC. These waveforms may differ significantly due to the power supply grid, whose capacitive and inductive components can modify both the frequency and magnitude components of the transient current. Given the complexity of today ICs, an accurate description of the circuit power grid is required to investigate the merits of transient current testing (idd(t)) approaches. In this work we develop and analyze a hierarchical power-grid equivalent circuit to evaluate the supply current frequency components and their distribution over the power/ground grid hierarchy. This is a key step to determine the feasibility of on-chip vs. off-chip idd(t) strategies and their posterior application to on-line testing.