Transistor Width Effect on the Power Supply Voltage Dependence of α-SER in CMOS 6T SRAM

Abstract

[eng] We present the experimental results on the impact of transistor width modulation and power supply voltage variation on the α-soft error rate (SER) in a 65-nm CMOS 6T static random access memory (SRAM) obtained from an accelerated test experiment using an Am-241 α-source. Five 6T cells with various combinations of transistor widths were tested and the results show that nMOS and pMOS widths play a different role on SER. We also found that the transistor width modulation effectiveness is highly dependent on the power supply voltage. In particular, the results show that at around nominal voltages, widening all pMOS while keeping all nMOS minimum sized, is the best way to improve SER. However, at lower voltages the results become completely different, and the best option for an overall SER improvement is to keep all transistors minimum sized.